FMS includes support for large pages on systems where they are available. Large pages improve performance of the virtual memory system. Large pages are selected using the FMS Parameters LPAGE and MDHOW.

Virtual memory systems must translate the virtual addresses of your code and data into physical memory addresses before the memory can be accessed. These translations must occur for each instruction and data element referenced.

Virtual addresses are divided into two parts: a page number and an offset within the page.

The low order part of the address, which is the offset within the page, is the same for both virtual and physical addresses. The high order part, which is the page number, is different for each page.

In order to perform page number translations at machine speed, a table, called the Translation Lookaside Buffer (TLB), is maintained of the most recently referenced pages. If the page requested is within this table, processing continues at machine speed. However, if the page is not found, a TLB miss occurs. This results in a significant interruption of the processing.

When a TLB miss occurs, the following actions are performed:

  1. The page table is scanned to determine if the requested page is in memory. If it is, its page number replaces one of the entries in the TLB and processing resumes.
  2. If the requested page is not in memory, a page fault occurs and the requested page is read in from disk. During this process, execution of the task is suspended.

The performance impact of frequent TLB misses can be significant, typically 5% or more on well-tuned applications.

The number of entries in the TLB is relatively small, usually about 100. Keep in mind that this table must be scanned within the machine cycle for every referenced instruction and data element. The address space spanned by all entries in the TLB is also relatively small. For example, if there are 100 entries and the page size is 4 Kbytes, the total address range that can be used without a TLB miss is 400 Kbytes. This address space includes your instructions, data and occasionally parts of the operating system. If your application repeatedly runs through an address range larger than that amount, TLB thrashing will occur.

On some systems it is possible to change the page size of the allocated memory to significantly reduce the number of TLB misses. For example, if the page size is increased to 16 Mbytes and there are 100 TLB entries, then the total address range becomes 1.5625 Gbytes. Small pages are efficient for editing or transaction processing. However they are inefficient for large scientific applications.